Interleaved and Concurrent NAND Operations — SSD Firmware Development — Part 7

To understand interleaving and concurrency for NAND operations, let’s recall the NAND operations without interleaving and concurrency. This time, we’ll need to put some timing characteristics for quantification. The time for these operations will definitely be different for different types of NAND (SLC, MLC, etc.) and even varies between different manufacturers. However, it is the relative time between the operations and stages of each operation that we will draw our attention to. I will use pseudo-real timing characteristics for our discussion.

Choosing a 40MHz clock for our channel-NAND communication, we have a cycle time of 25ns. For a read page operation, we can look at the following table.

Figure 1 — Read page timing

Note that the device busy time is independent of the clock. We are choosing 50us here and we are reading 8192 bytes from the page. We effectively get approximately 30.64MiB/s of bandwidth. Let’s take a look at what a logic analyzer might look like if we capture the signals and do a read of 2 pages on the same NAND device.

As we can see, every time the NAND device goes busy, the channel is idle. Now…