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SSD Firmware Development — Part 6— NAND Operations Breakdown
Earlier in the series, we’ve learned the composition of NAND in terms of pages and blocks and the 3 pillar operations: read, write, and erase. In this part, we will explore and breakdown these 3 operations in more detail.
From a hardware perspective, a NAND device is connected to a controller via “buses” that make up the essentials of the communication medium between the controller and the NAND device. These are the essential signals:
- CLE (command latch enable)
- ALE (address latch enable)
- CE (chip enable)
- DATA (data lines)
- R/B (ready/busy line)
There are other signals that are quite important as far as hardware is concerned (such as CLK or DQS, WE, RE, etc.), but for now, the above mentioned are sufficient for our discussion.
What we need to be aware of here is that a NAND operation involves a series of “micro-commands” issued to the NAND device via the controller, with certain timing characteristics. Usually the controller will take care of the minute timing manipulation for the signals, but sometimes we can configure the controller to change these timing, to work out some nuisance for certain NAND-Controller compatibility issues for example. There are also some timing characteristics a firmware developer should be aware of for debugging and performance investigation.
